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Features
* 3.0V to 3.6V Read/Write * Burst Read Performance
- <100 MHz (RAS Latency = 2, CAS Latency = 6), 10 ns Cycle Time tSAC = 7 ns - <75 MHz (RAS Latency = 2, CAS Latency = 5), 13 ns Cycle Time tSAC = 8 ns - <50 MHz (RAS Latency = 1, CAS Latency = 4), 20 ns Cycle Time tSAC = 9 ns MRS Cycle with Address Key Programs - RAS Latency (1 and 2) - CAS Latency (2 ~ 8) - Burst Length: 4, 8 - Burst Type: Sequential and Interleaved Word Selectable Organization - 16 (Word Mode)/x 32 (Double Word Mode) Sector Erase Architecture - Eight 256K Word or 128K Double Word (4-Mbit) Sectors Independent Asynchronous Boot Block - 8K x 16 Bits with Hardware Lockout Fast Program Time - 3-volt, 100 s per Word/Double Word Typical - 12-volt, 30 s per Word/Double Word Typical Fast Sector Erase Time - 2.5 Seconds at 3 Volts - 1.6 Seconds at 12 Volts Low-power Operation - ICC Read = 75 mA Typical Input and Output Pin Continuity Test Mode Optimizes Off-board Programming Package: - 86-pin TSOP Type II with Off-center Parting Line (OCPL) for Improved Reliability LVTTL-compatible Inputs and Outputs
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* * * * * * * * *
32-megabit (1M x 32 or 2M x 16) High-speed Synchronous Flash Memory AT49LD3200 AT49LD3200B SFlashTM
Description
The AT49LD3200 or AT49LD3200B SFlashTM is a synchronous, high-bandwidth Flash memory fabricated with Atmel's high-performance CMOS process technology and is organized either as 2,097,152 x 16 bits (word mode) or as 1,048,576 x 32 bits (double word mode), depending on the polarity of the WORD pin (see Pin Function Description Table). Synchronous design allows precise cycle control. I/O transactions are possible on every clock cycle. All operations are synchronized to the rising edge of the system clock. The range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high-bandwidth, high-performance memory system applications. The AT49LD3200B will automatically activate the Asynchronous Boot Block after power-up, whereas with the AT49LD3200, the Asynchronous Boot Block can be activated through Mode Register Set. The synchronous DRAM interface allows designers to maximize system performance while eliminating the need to shadow slow asynchronous Flash memory into highspeed RAM. The 32-megabit SFlash device is designed to sit on the synchronous memory bus and operate alongside SDRAM.
Rev. 1940B-FLASH-11/01
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To maximize system manufacturing throughput the AT49LD3200(B) features highspeed 12-volt program and erase options. Additionally, stand-alone programming cycle time of individual devices or modules is optimized with Atmel's unique input and output pin continuity test mode.
Pin Configuration
TSOP (Type II) Top View
VCC DQ0 VCCQ DQ16 DQ1 VSSQ DQ17 DQ2 VCCQ DQ18 DQ3 VSSQ DQ19 MR VCC DQM NC CAS RAS CS WORD A12 A11 A10 A0 A1 A2 NC VCC NC DQ4 VSSQ DQ20 DQ5 VCCQ DQ21 DQ6 VSSQ DQ22 DQ7 VCCQ DQ23 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
VSS DQ31 VSSQ DQ15 DQ30 VCCQ DQ14 DQ29 VSSQ DQ13 DQ28 VCCQ DQ12 NC VSS NC VPP WE CLK CKE A9 A8 A7 A6 A5 A4 A3 NC VSS NC DQ27 VCCQ DQ11 DQ26 VSSQ DQ10 DQ25 VCCQ DQ9 DQ24 VSSQ DQ8 VSS
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AT49LD3200(B)
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AT49LD3200(B)
Pin Function Description
Pin CLK CS CKE Name System Clock Chip Select Clock Enable Input Function Active on the rising edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK and CKE. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for powerdown in standby mode. Row/column addresses are multiplexed on the same pins. Row address: RA0 ~ RA12, Column address: CA0 ~ CA6 (x32), CA0 ~ CA7 (x16) Latches row addresses on the rising edge of the CLK with RAS low. Enables row access. Latches column addresses on the rising edge of the CLK with CAS low. Enables column access. Enables mode register set with MR low. (Simultaneously CS, RAS and CAS are low). Data input for program/erase. Data output for read. Power and ground for the input buffers and the core logic. Power and ground for the output buffers. Double word mode/word mode, depending on polarity of WORD pin (WORD = high, double word mode; WORD = low, word mode). Should be set to the desired state during power-up and prior to any device operation. Masks output operation when a complete burst is not required. Not connected Enables the chip to be written. Program/Erase power supply.
A0 - A12 RAS CAS MR DQ0 - DQ31 VCC/VSS VCCQ/VSSQ WORD
Address Row Address Strobe Column Address Strobe Mode Register Set Data Input/Output Power Supply/Ground Data Output Power/Ground x32/x16 Mode Selection
DQM NC WE VPP
Data-out Masking No Connection Write Enable Program/Erase Pin Supply
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Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground .....................................-0.6V to +4.6V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on VPP with Respect to Ground ...................................-0.6V to +13.5V Power Dissipation .............................................................. 1 W *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Functional Block Diagram
DQ0 DQ16 IO Buffer DQ15 DQ31
WE VPP
Program/ Erase Logic
ADD Row Decoder Row Buffer
8K x 16 Boot Block Sense AMP
Address Register CLK
CLK ADD
1M x 32 Cell Array
LRAS Column Buffer
Column Decoder
LCKE
Latency & Burst Length
LRAS
LMR LCAS Timing Register
Programming Register
CKE
MR
RAS
CAS
CS
DQM
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AT49LD3200(B)
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AT49LD3200(B)
DC and AC Operating Range
AT49LD3200(B)-10 Operating Temperature (Case) VCC, VCCQ Power Supply Commercial Industrial 0C - 70C -40C - 85C 3.0V to 3.6V AT49LD3200(B)-13 0C - 70C -40C - 85C 3.0V to 3.6V AT49LD3200(B)-20 0C - 70C -40C - 85C 3.0V to 3.6V
DC Characteristics
Symbol ISB1 ISB2 ISB3 ICC IIL IOL VIH VIL VOH VOL Notes: Parameter VCC Standby Current CMOS VCC Standby Current TTL VCC Active Standby Current VCC Active Current Input Leakage Current Output Leakage Current (IOOUT Disabled) Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level (Logic 1) Output Low Voltage Level (Logic 0) Condition CKE = 0, tCC = Min CKE VIL (Max), tCC = Min CS VIH (Min), tCC = Min tCC = Min, All Outputs Open 0V VIN VDD + 0.3V Pins not under test = 0V (0V VOUT VDD Max) All Outputs in High-Z Note(1) Note(2) IOH = -2 mA IOL = 2 mA -10 -10 2.0 -0.3 2.4 0.4 Min Max 20 20 50 150 10 10 VDD + 0.3 0.8 Units mA mA mA mA A A V V V V
1. VIH (max) = 4.6V for pulse width <10 ns acceptable, pulse width measured at 50% of pulse amplitude. 2. VIL (min) = -1.5V for pulse width <10 ns acceptable, pulse width measured at 50% of pulse amplitude.
AC Operating Test Conditions
TA = 0 to 70C, VCC = 3.3V 0.3V, unless otherwise noted.
Parameter(1) Timing Reference Levels of Input/Output Signals Input Signal Levels Transition Time (Rise & Fall) of Input Signals Output Load Note: Value 1.4V VIH/VIL = 2.4V/0.4V tr/tf = 1 ns/1 ns LVTTL
1. If CLK transition time is longer than 1 ns, timing parameters should be compensated. Add [(tr + tf)/2-1] ns for transition time longer than 1 ns. Transition time is measured between VIL (max) and VIH (min).
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Figure 1. DC Output Load Circuit
3.3V
1200 Output 870 50 pF V OH (DC) = 2.4V, I OH= -2 mA V OL (DC) = 0.4V, I OL= 2 mA
Figure 2. AC Output Load Circuit
Vtt = 1.4V
50 Output Z0 = 50 50pF
Pin Capacitance(1)
f = 1 MHz, T = 25C
Symbol CIN COUT
(2)
Typ 4 8
Max 6 12
Units pF pF
Conditions VIN = 0V VOUT = 0V
Notes:
1. This parameter is characterized and is not 100% tested. 2. VPP behaves as an output pin.
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AT49LD3200(B)
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AT49LD3200(B)
AC Read Characteristics
AC operating conditions unless otherwise noted.
<100 MHz Symbol tCC tSAC tOH tCH tCL tRC tSS tSH tSLZ tSHZ tT tVCVC Notes: Parameter CLK Cycle Time CLK to Valid Output Delay Data Output Hold Time CLK High Pulse Width CLK Low Pulse Width Row-active to Row-active Input Setup Time Input Hold Time CLK to Output in Low-Z CLK to Output in High-Z Transition Time Valid CAS Enable to Valid CAS Enable(2) 0.1 9
(1)
<75 MHz Min 13 Max
<50 MHz Min 20 Max Units ns 9 4 6.5 6.5 9 4 2 0 ns ns ns ns clks ns ns ns 15 0.1 7 10 ns ns clks
Min 10
Max
7 3 3 3 11 2 1 0 7 10 0.1 8 4 4 4 10 4 2 0
8
10 10
1. These tRC values are for BL = 8. For BL = 4, tRC = 7 CLKs for up to 100 MHz, tRC = 6 CLKs for up to 75 MHz, tRC = 5 CLKs for up to 50 MHz. RAS latency increase means a simultaneous tRC increase in the same number of cycles. (If RAS latency is 3 CLKs, tRC is 12 CLKs for BL = 8.) Refer to page 27 for gapless operation. 2. These tVCVC values are for BL = 8. For BL = 4, tVCVC = 5 CLKs for up to 100 MHz, tVCVC = 4 CLKs for up to 75 MHz, tVCVC = 3 CLKs for up to 50 MHz. Refer to page 27 for gapless operation.
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Function Truth Table
(V = Valid, X = Don't Care, H = Logic High, L = Logic Low)
Abbreviations (RA: Row Address, CA: Column Address, NOP: No Operation Command, DWM: Double Word Mode, WM: Word Mode)
Command Register
(1)
CKEn-1 Mode Register Set Row Access & Latch Column Access & Latch H H H H
CKEn X X X X X L H X X X X X X X X X X X
CS L L L L L X X X H L L L L H L L L X
RAS L L H H L X X X X H H H H X L H H X
CAS L H L H H X X X X H L L L X L L L X
MR(9) L H H L L X X X X H H X X X L H X X
DQM X X X X X X X V X X X X X X X X X X
Add. Code RA CA X X X X X X X CA
WORD X X X X X X X X X X H
VPP X X X X X X X X X X X
WE X X H X X X X X X X H L L X X H L X
Row Active Read
Burst Stop
(Precharge on Synch. DRAM) Two Standby Mode Entry Exit
H H L H H H
Power-down and Clock Suspend(2) DQM(3)
No Operation Command(4)
Organization Control(5) Program/Erase(6) Fast Program/Erase
(6)
H H H H H H Entry H X
L CA CA X A7 = H L CA Code
(8)
X X X X X X X
X 12V X X X X X
Program/Erase Inhibit Product Identification(7) Mode Register Set Read
Continuity Test Mode Exit Notes:
1. A0 ~ A6: Program keys (@MRS). After power-up, mode register set can be set before issuing other input command. After the Mode Register Set command is completed, no new commands can be issued for 3 CLK Cycles, and CS or MR state must be defined "H" within 3 CLK cycles. Refer to the Mode Register Control Table. 2. In the case CKE is low, two standby modes are possible. Those are standby mode in power-down, and active standby mode in clock suspend (non-power-down). Power-down: CKE = "L" (after no command is issued for 60 s) Clock Suspend: CKE = "L" (at the range of Row Active, Read and Data Out) 3. DQM sampled at rising edge of a CLK makes a high-Z state the data-out state, delayed by 2 CLK cycles. 4. Precharge command on Synch. DRAM can be used for Burst Stop operation during burst read operation only. 5. Mode selection is controlled by the polarity of WORD pin, "H" state is DWM, "L" state is WM. WORD should be set to the desired state during power-up and prior to any device operation. 6. Data is provided through DQ0 ~ DQ31. Refer to AC programming and erasing waveforms. 7. DQ0 ~ DQ31 will output Manufacturer Code/Device Code. 8. A0 = A2 = A11 = "H", A1 = A10 = A12 = "L" 9. The user can tie MR and WE together to simplify the interface of the AT49LD3200(B) onto the standard SDRAM bus.
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AT49LD3200(B)
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AT49LD3200(B)
Asynchronous Boot Block Function Truth Table
Command Read Output Disable Program/Erase
(1) (1)
CLK(2) X X
CKE(2) X X H H H
CS L L L L H
RAS X X H H X
CAS X X L L X
MR X X X X X
DQM L H X X X
Add. Add X Add Add X
WORD X X X X X
VPP X X X 12V X
WE X X L L X
Fast Program/Erase
Program/Erase Inhibit Notes:
1. Program/Erase is performed through the synchronous bus cycle operation after the boot block is activated through either power-up or Mode Register Set. 2. It is recommended to hold CKE Low if CLK is running during asynchronous boot block mode except for synchronous command cycle and MRS operations.
Mode Register Control Table(1)
Register Programmed with MRS
Address Function A7 Product ID A6 RAS Latency A5 A4 CAS Latency A3 A2 Burst Type A1 A0 Burst Length
Product ID A7 0 1 "Read" Array ID A6 0 1
RAS Latency Type 1 2 A5 0 0 0 0 1 1 1 1
CAS Latency A4 0 0 1 1 0 0 1 1 A3 0 1 0 1 0 1 0 1 Length Reserved 2 3 4 5 6 7 8 A2 0 1
Burst Type Type Sequential Interleave A1 0 0 1 1
Burst Length A0 0 1 0 1 Length Reserved 4 8 Boot Block
Note:
1. After power-up, when the user wants to change Mode Register Set, the user must exit from power-down mode and start Mode Register Set before entering normal operation mode. Reserved modes are not to be used; device function in these modes is not guaranteed.
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Addressing Map
WORD = "H": x32 Organization(1)
Function Row Address Column Address Note: A0 RA0 CA0 A1 RA1 CA1 A2 RA2 CA2 A3 RA3 CA3 A4 RA4 CA4 A5 RA5 CA5 A6 RA6 CA6
(1)
A7 RA7 X
A8 RA8 X
A9 RA9 X
A10 RA10 X
A11 RA11 X
A12 RA12 X
1. Column Address MSB (at x32 organization) (X = Don't Care)
WORD = "L": x16 Organization(1)
Function Row Address Column Address Note: A0 RA0 CA0 A1 RA1 CA1 A2 RA2 CA2 A3 RA3 CA3 A4 RA4 CA4 A5 RA5 CA5 A6 RA6 CA6 A7 RA7 CA7
(1)
A8 RA8 X
A9 RA9 X
A10 RA10 X
A11 RA11 X
A12 RA12 X
1. Column Address MSB (at x16 organization) (X = Don't Care)
Each Address is Arranged as Follows(1)(2)
For X32 operation, MSB Address Register Address AR19 RA12 AR18 RA11 AR17 RA10 ... ... AR8 RA1 AR7 RA0 AR6 CA6 ... ... AR3 CA3 AR2 CA2 AR1 CA1 BL = 4 * Initial Address Notes: BL = 8 LSB AR0 CA0
1. For X16 operation, when CA0 is set to Low, data belonging to 0 ~ 15th registers are output to DQ0 ~ DQ15 pins, and when CA0 is set to High, data belonging to 16 ~ 31th registers are output to DQ0 ~ DQ15 pins. 2. Asynchronous Boot Block uses x16 operation and A0 ~ A12 as address inputs.
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AT49LD3200(B)
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AT49LD3200(B)
Burst Sequence (Burst Length = 4)
Initial Address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 Sequential 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 Interleave 2 3 0 1 3 2 1 0
Burst Sequence (Burst Length = 8)
Initial Address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
Device Operations
Clock (CLK)
A square wave signal (CLK) must be applied externally at cycle time tCC. All operations are synchronized to the rising edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high, all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around the positive edge of the clock for proper functionality and ICC specifications. The clock enable (CKE) gates the clock into the AT49LD3200(B) and is asserted high during all cycles, except for power-down, standby and clock suspend mode. If CKE goes low synchronously with clock (setup and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen for as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. The AT49LD3200(B) remains in the power-down mode, ignoring other inputs for as long as CKE remains low. The power-down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1 CLK + tSS" before the rising edge of the clock, then the AT49LD3200 becomes active from the same clock edge accepting all the input commands. When RAS, CAS and MR are high, the AT49LD3200(B) performs no operation (NOP). NOP does not initiate any new operation. Device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, MR
Clock Enable (CKE)
NOP and Device Deselect
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and all the address inputs are ignored. In addition, entering a Mode Register Set command in the middle of a normal operation results in an illegal state in the AT49LD3200(B).
Power-up
The following power-up sequence is recommended. 1. Apply power and start clock. Hold the MR, CKE and DQM inputs high; all other pins are a NOP condition at the inputs before or along with VCC (and VCCQ) supply. 2. Set WORD to the desired state (prior to any device operation). 3. To change the default Mode Register Set values, perform a Mode Register Set cycle to program the RAS latency, CAS latency, burst length and burst type. 4. At the end of three clock cycles after the mode register set cycle, the device is ready for operation. When the above sequence is used for power-up, all outputs will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence. For AT49LD3200B, Asynchronous Boot Block will be selected after power-up.
Mode Selection Control
Mode selection is controlled by the polarity of WORD pin. WORD should be set to the desired state during power-up and prior to any device operation. The AT49LD3200(B) can be organized as either double word wide (x32) or word wide (x16). The organization is selected via the WORD pin. When WORD is asserted high (VIH), the double wordwide organization is selected. When WORD is asserted low (VIL), the word-wide organization is selected. The address bits required to decode one of the available cell locations out of the total depth are multiplexed onto the address select pins and latched by externally applying two commands. The first command, RAS asserted low, latches the row address into the device. A second command, CAS asserted low, subsequently latches the column address.
Address Decoding
Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of
AT49LD3200(B). It programs the RAS latency, CAS latency, burst length, burst type, s e l e c t s p r o d u c t ID R e a d o r ac ti v a te s t h e A s y n c h r on o u s B o o t B l o c k . Fo r AT49LD3200(B), the default value of the mode register is defined as array read with RAS latency = 2, CAS latency = 5, burst length = 4, sequential burst type. When and if the user wants to change its values, the user must exit from power-down mode and start Mode Register Set before entering normal operation mode. The mode register is reprogrammed by asserting low on CS, RAS, CAS and MR (the AT49LD3200(B) should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ A7 in the same cycle as CS, RAS, CAS and MR going low is the data written in the mode register. Three clock cycles are required to complete the program in the mode register, therefore after a Mode Register Set command is completed, no new commands can be issued for 3 clock cycles and CS or MR must be high within 3 clock cycles. The mode register is divided into various fields, depending on functionality. The burst length field uses A0 ~ A1, burst type uses A2, CAS latency (read latency from column address) uses A3 ~ A5, RAS latency uses A6 (RAS to CAS delay), array read or product ID read uses A7. Refer to Mode Register Control Table for specific codes for various burst lengths, burst types, CAS latencies, RAS latencies, and read modes.
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AT49LD3200(B)
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AT49LD3200(B)
Latency
There are latencies between the issuance of a Row Active command and when data is available on the I/O buffers. The RAS to CAS delay is defined as the RAS latency. The CAS to data out delay is the CAS latency. The CAS and RAS latencies are programmable through the mode register. RAS latencies of 1 and 2, and CAS latencies of 2 through 6 are supported. It is understood that some RAS and CAS latency values are reserved for future use, and are not available in this generation of synchronous Flash. The following are the supported minimum values: RAS latency = 2, and CAS latency = 6 for 100 MHz operation, and RAS latency = 2, and CAS latency = 5 for 66 MHz operation, and RAS latency = 1, and CAS latency = 4 for 50 MHz operation, and RAS latency = 1, and CAS latency = 3 for 33 MHz operation. The DQM is used to mask output operations when a complete burst read is not required. It works similar to OE during a read operation. The read latency is two cycles from DQM, which means DQM masking occurs two cycles later in the read cycle. DQM operation is synchronous with the clock. The masking occurs for a complete cycle. (Also refer to the DQM timing diagram.) The Burst Read command is used to access a burst of data on consecutive clock cycles from an active row state. The Burst Read command is issued by asserting low CS and CAS with MR being high on the rising edge of the clock. The first output appears in CAS latency number of clock cycles after the issuance of the Burst Read command. The burst length, burst sequence and latency from the Burst Read command are determined by the mode register, which is already programmed. Burst read can be initiated on any column address of the active row. The output goes into high-impedance at the end of the burst, unless a new burst read is initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read. Before a word/double word can be reprogrammed, it must be erased. The erased state of the memory bits is a logical "1". The AT49LD3200(B) is organized into eight uniform four megabit sectors (SA0 - SA7) that can be individually erased. The Sector Erase command is a synchronous six-bus cycle operation (refer to the Command Definition table and Program Cycle and Erase Cycle waveforms). The erase code consists of 6byte (DQ8 - DQ31 are Don't Care inputs for the command) load commands to specific address locations with a specific data pattern. The sector address and 30H data input are latched in the sixth cycle. The sector erase starts at the following rising edge of CLK after the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. Any commands written to the device during the erase cycle will be ignored. The maximum time needed to erase one sector is tEC.
DQM Operation
Burst Read
Sector Erase
Word/Double Word Programming
Once a sector is erased, it is programmed (to a logical "0") on a word-by-word/doubleword-by-double-word basis. Programming is accomplished via the internal device command register and is synchronous four-bus cycle operation (refer to the Command Definition table and Program Cycle and Erase Cycle waveforms). The programming operation starts at the following rising edge of CLK after the fourth cycle. The device will automatically generate the required internal program pulses. Any commands written to the device during the embedded programming cycle will be ignored. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is completed after the specified tPGM cycle time. The DATA polling feature may also be used to indicate the end of a program cycle.
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Product Identification
The product identification mode identifies the device and manufacturer as Atmel. This mode can be used by an on-board controller or external programmer to identify the correct programming algorithm for the Atmel product. The AT49LD3200(B) features DATA polling to indicate the end of a program or sector erase cycle. DATA polling may begin at any time during the program or sector erase cycle. During a program cycle, an attempted read of the last word/double word loaded will result in the complement of the loaded data in DQ7. Once the program cycle has completed, true valid data can be read on all outputs and the next cycle may begin. During a sector erase operation, an attempt to read the device will give a "0" on DQ7. Once the sector erase cycle has completed, logical "1" data can be read on all outputs from the device.
DATA Polling
Hardware Data Protection
Hardware features protect against inadvertent programming or erasure to the AT49LD3200(B) in the following way: VCC sense: if VCC is below 2.3V (typical), the program or erase function is inhibited; but if VCC dips below 2.3V during program or erase cycle, the respective function will be interrupted and the data at the location being programmed may be corrupted. The AT49LD3200(B) has built-in circuitries to make input and output pin continuity check simple and easy. This mode can be activated via the internal device command register and is a synchronous five-bus cycle operation (refer to the Command Definition Table and Continuity Test Mode Entry Waveforms). After the bus cycle operation, keep DQM high (VIH) and allow 5 sec for circuit setup time or until data is no longer asserted at DQ0 - DQ7, whichever takes longer. This will keep DQ0 - DQ7 from contention since data is asserted at DQ0 - DQ7 during the mode entry sequence. Then DQM can be asserted low (VIL) to enable DQ0 - DQ7 for test. Once in this asynchronous mode, input pins are virtually tied to output pins internally forming input - output pin pairs. The output pin of the pair will follow the logic state of the input pin of the pair (refer to the Input Output Pin Pairs table). To exit the mode, A0, A2 and AII are asserted high (VIH) and A1, A10 and A12 are asserted low (VIL), allow 5 sec for circuit recovery time before returning the device for normal operation.
Continuity Test Mode
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AT49LD3200(B)
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AT49LD3200(B)
Input - Output Pin Pairs
Input MR RAS CAS DQM CS WORD A12 A11 A10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CKE CLK WE VPP Output DQ0, DQ16 DQ1, DQ17 DQ2 DQ18 DQ3 DQ19 DQ4 DQ20 DQ5 DQ21 DQ6, DQ22 DQ7, DQ23 DQ8, DQ24 DQ9, DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 DQ13, DQ29 DQ14, DQ30 DQ15, DQ31
Asynchronous Boot Block
The AT49LD3200B will automatically activate the Asynchronous Boot Block after power-up and the AT49LD3200 can activate the Asynchronous Boot Block through the Mode Register Set. The size of the boot block is 8K x 16 bits with addresses A0 ~ A12 and outputs DQ0 ~ DQ15. The contents of the boot block are accessed asynchronously, meaning the data at outputs will change according to the address inputs after tACC, without any external clocking signals. Programs and erases are performed using the synchronous bus cycle operation (refer to Command Definitions table and Program Cycle and Erase Cycle waveforms) after the boot block is activated either through power-up or Mode Register Set. Programming of the boot block is set up for x16 mode. This Asynchronous Boot Block has a lockout feature that prevents programming or erasing of data in this boot block once the feature has been enabled. This feature does not have to be activated; the boot block's usage as a protected region is optional to the user. Once this feature is enabled, the data in the boot block can no longer be erased or programmed when input levels of 3.6V or less are used. To activate the lockout feature,
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1940B-FLASH-11/01
Boot Block Lockout command, which is a synchronous five-bus cycle operation, must be performed (refer to Command Definitions table and Program Cycle Waveforms). A software method is available to determine if programming or erasing of the boot block is locked out. Issue Boot Block Lockout Verify command and observe DQ0 ~ DQ7. If the data show 00H/02H, the boot block can be programmed or erased; if the data show 01H/03H, the lockout feature has been enabled and the boot block cannot be programmed or erased. The Boot Block Lockout Verify Exit command should be used to return to standard operation (refer to Command Definition table and Boot Block Lockout Verify Waveforms). The user can override the boot block lockout by taking the MR pin to 12 volts after the boot block is activated. When the MR pin is brought back to TTL levels, the boot block lockout feature is again active.
16
AT49LD3200(B)
1940B-FLASH-11/01
AT49LD3200(B)
Command Definition in Hex(1)
Command Sequence Word/ Double Word Program Sector Erase Continuity Test Mode Entry Boot Block Lockout Boot Block Lockout Verify Boot Block Lockout Verify Exit Bus Cycles 1st Bus Cycle RA CA Data 2nd Bus Cycle RA CA Data 3rd Bus Cycle RA CA Data 4th Bus Cycle RA CA Data 5th Bus Cycle RA CA Data 6th Bus Cycle RA CA Data
4
AA
55
AA
55
2A
55
AA
55
A0
RA
CA
DIN
6
AA
55
AA
55
2A
55
AA
55
80
AA
55
AA
55
2A
55
SA(2)
X
30
5
AA
55
AA
55
2A
55
AA
55
80
AA
55
AA
AA
55
70
5
AA
55
AA
55
2A
55
AA
55
80
AA
55
AA
AA
55
40
5
AA
55
AA
55
2A
55
AA
55
80
AA
55
AA
AA
55
90
5
AA
55
AA
55
2A
55
AA
55
80
AA
55
AA
AA
55
F0
Notes:
1. The DATA FORMAT in each bus cycle is as follows: DQ31 - DQ8 (Don't Care); DQ7 - DQ0 (Hex). 2. SA = Sector Addresses: Any word/double word address within a sector can be used to designate the sector address. See Sector Address Mapping table below. 3. Allow minimum 200 ns after Boot Block Lockout Verify command and before Read. 4. Allow minimum 10 s after Boot Block Lockout Verify Exit command for the device to return to standard operation.
Sector Address Mapping
x16 Address Range Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 Size (Word/Double Word) 256K/128K 256K/128K 256K/128K 256K/128K 256K/128K 256K/128K 256K/128K 256K/128K CA7-0 X X X X X X X X RA12-0 00XX 03XX 04XX 07XX 08XX 0BXX 0CXX 0FXX 10XX 13XX 14XX 17XX 18XX 1BXX 1CXX 1FXX x32 Address Range CA6-0 X X X X X X X X RA12-0 00XX 03XX 04XX 07XX 08XX 0BXX 0CXX 0FXX 10XX 13XX 14XX 17XX 18XX 1BXX 1CXX 1FXX
17
1940B-FLASH-11/01
Basic Feature and Function Descriptions
MRS
Mode Register Set CLK CMD MRS
(1) 3CLK
ACT
Clock Suspend
Clock Suspended During Burst Read (BL=4) CLK CMD CKE
Masked by CKE
RD
Internal CLK
Data
DQ0
D0 DQ1
DQ2
DQ3
Suspended Dout
: This command cannot be activated.
Clock Suspend Exit and Power-down Exit
1) Clock Suspend Exit CLK CKE Internal CLK CMD RD
tSS
2) Power Down CLK CKE Internal CLK CMD NOP ACT
tSS
Note:
After Mode Register Set command is completed, no new commands can be issued for 3 clock cycles, and MR or CS should be fixed "H" within a minimum of 3 clock cycles.
18
AT49LD3200(B)
1940B-FLASH-11/01
AT49LD3200(B)
DQM Operation
1) Read Mask (BL=4) CLK CMD DQM Data(CL2) Data(CL3) Data(CL4) DQ0 DQ1 DQ0
Masked by DQM High-Z
RD
DQ3
High-Z High-Z
DQ2 DQ1
DQ 3 DQ2 DQ3
DQM to Data-out Mask = 2CLKs 2) DQM with Clock Suspended (BL=8) CLK CMD CKE DQM
(1)
RD
Data(CL2) Data(CL3) Data(CL4)
DQ0
D1DQ1 DQ0
High-Z High-Z High-Z
DQ 3 DQ2 DQ 1
High-Z High-Z High-Z
DQ 5 DQ4 DQ3
High-Z High-Z High-Z
DQ7 DQ6 DQ7 DQ5 DQ6 DQ7
Note:
DQM makes data out high-Z after 2 CLKs, which should be masked by CKE "L".
19
1940B-FLASH-11/01
Read Cycle I: Normal @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
tCH
0 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tCL tCC
CKE
tRC tSH
HIGH
CS
RAS Latency tSH tSS
RAS
tSS
CAS
tSH
ADDR
RAa tSS
CAa
RAb
CAb
tRC=6 clocks at BL=4
(1)
tOH
Data
DQa0 DQa1 DQa2 DQa3 tSAC tSHZ
DQb0 DQb1 DQb2 DQb3
MR
Row Active
Read
Row Active
Read
: Don't Care
Note:
When the burst length is 4 at 66 MHz, tRC is equal to 6 clock cycles.
20
AT49LD3200(B)
1940B-FLASH-11/01
AT49LD3200(B)
Read Cycle II: Consecutive Column Access @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
tCH
0 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tCL tCC
CKE
HIGH
tSH
CS
RAS Latency tSH tSS
RAS
tSS
CAS
tSH
ADDR
RAa tSS
CAa
CAb
tVCVC=4 clocks at BL=4 tOH
Data
Burst Length=4
DQa0 DQa1 DQa2 DQa3 DQb0 DQb1 DQb2 DQb3 tSAC tSHZ
MR
Row Active
Read
Read : Don't Care
Note:
When column access is initiated beyond tVCVC, at BL = 4, CAa access read is completed, CAb access read begins.
21
1940B-FLASH-11/01
Read Cycle III: Clock Suspend @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
0 CLK
tCL tCC
1
2
3
tCH
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
(1)
Internal CLK
CS
RAS Latency tSH
RAS
tSS
CAS
tSH
ADDR
RAa tSS
CAa
tVCVC= 4 clocks at BL=4
(2)
Data
Burst Length=4
DQa0
DQa1
DQa2 DQa3
MR
Row Active
Read
Clock Suspend Resume : Don't Care
Notes:
1. From next clock after CKE goes low, clock suspension begins. 2. For clock suspension, data output state is held and maintained.
22
AT49LD3200(B)
1940B-FLASH-11/01
AT49LD3200(B)
Read Interrupted by Precharge Command and Burst Read Stop Cycle @Burst Length = 8
0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
CAb
(1)
(1) DQb0 DQb1 DQb2 DQb3 DQb4 DQb5
CL=2 Data CL=3
DQa0 DQa1 DQa2 DQa3 DQa4
(2) DQa0 DQa1 DQa2 DQa3 DQa4
(2) DQb0 DQb1 DQb2 DQb3 DQb4 DQb5
MR
DQM
(1)(2)
Row Active
Read
Burst Stop
Read
Precharge
: Don't Care
Notes:
1. The Burst Stop command is valid at every page burst length. The data bus goes to high-Z after the CAS latency from the Burst Stop command is issued. 2. The interval between Read command (column address presented) and Burst Stop command is 1 cycle (min).
23
1940B-FLASH-11/01
Power-down and Clock Suspend Cycle: @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
tSS
CKE
(1)
(1)
Power Down
Clock Suspend
(3)
CLK
(internal)
CS
RAS
CAS
(2)
tSH NOP RAa tSS CAa
ADDR
Data
Data High-Z State
DQa0 DQa1
DQa2
DQa3
MR
(High)
Row Active Power-down Entry Power-down Exit
Read Clock Suspend Entry Clock Suspend Exit : Don't Care
Notes:
1. From next clock after CKE goes low, clock suspend and power-down begins. 2. After power-down exit, NOP should be issued and new command can be issued after 1 clock. 3. Clock suspend is in active standby mode.
24
AT49LD3200(B)
1940B-FLASH-11/01
AT49LD3200(B)
Mode Register Set: @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
tCH
0 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tCC
tCL
CKE
HIGH
tSH
CS
tSS
RAS
CAS
ADDR
Code
RAa
CAa
Data
Data High-Z State
DQa0 DQa1 DQa2 DQa3
MR
MRS
Row Active : Don't Care
Notes:
1. After the Mode Register Set is completed, no new commands can be issued for 3 CLK cycles. 2. After power-up, necessarily Mode Register Set should be completed at least one time and CS or MR must be fixed "H" within 3 clock cycles, and when user wants to change Mode Register Set, user must exit from power-down mode and start Mode Register Set before chip enters normal operation mode.
25
1940B-FLASH-11/01
Detailed Functional Truth Table
Current State After Power-up(1) Input Signal CKE L H H H Row Active H H L CS X L L L L L X RAS X L L L H L X CAS X H L H L L X MR X H L H H L X Add. X RA Code RA CA Code X Next State Operation Power-down Row Active; latch RA Mode Register Set If consecutive row access is issued within tRC (min.) without CAS enabling, only the final RA is valid. Begin READ; latch CA Illegal(1) Clock Suspend Row Access in Read State, within the tRC, previous read is ignored and new row is activated. Beyond the tRC, previous read is completed and new read begins. Consecutive Column Access, within the tVCVC, only the final CA is valid and the previous burst read is ignored. Beyond the tVCVC, the previous read is completed and new read begins. NOP (after Burst Read)/Read Interrupt NOP (after Burst Read)/Read Interrupt Illegal(1) Clock Suspend/Power-down Low Power Consumption Mode NOP Illegal Illegal
H
L
L
H
H
RA
H READ H H H L Any State Any State Any State H Note: L H H
L
H
L
H
CA
L L L X L L L L
L H L X L H L H
H H L X L H L L
L L L X H H H L
X X Code X X X X CA
1. After the power-up, when user wants to change MR Set, user must exit from power-down mode and start MR Set before chip enters normal operation mode.
26
AT49LD3200(B)
1940B-FLASH-11/01
AT49LD3200(B)
Technical Notes
Frequency vs. AC Parameter Relationship Table(1)
<100 MHz Burst Length 4 RAS Latency 2 7 6 8 2 7 12 10 8 11 6 9(2) CAS Latency 6 tRC (min) 7 tVCVC (min) 5(2)
<75 MHz Burst Length 4 RAS Latency 2 6 5 8 2 6 11 9 7 10 5 8(2) CAS Latency 5 tRC (min) 6 tVCVC (min) 4(2)
<50 MHz Burst Length RAS Latency CAS Latency 4 4 1 5 6 4 8 1 5 6 Notes: tRC (min) 4
(2)
tVCVC (min) 3/4(2) 4(2) 5 7/8(2) 8(2) 9
5 6 8(2) 9 10
1. Above tables are not specifications values, but rather the actual number of clock cycles. There are no gapless operations for CAS latency 7 and 8. 2. Minimum clocks for gapless operation. 3. tRC (max) = tVCVC (max) = 50 s. If tRC (max) or tVCVC (max) has been reached, a new "ACTIVE" command is necessary for new access.
27
1940B-FLASH-11/01
CAS Interrupt
Read interrupted by Read (BL=4) (1) CLK CMD ADD Data(CL2) Data(CL3) Data(CL4)
(2)
RD A
RD B DQB0 DQB1 DQB2 DQB3 DQB0 DQB1 DQB2 DQB3 DQB0 DQB1 DQB2 DQB3
Notes:
1. By "Interrupt", it is meant to stop Burst Read by external command before the end of burst. By "CAS Interrupt", to stop Burst Read by CAS access. 2. CAS to CAS delay (=1 CLK).
Read Interrupt Operation by Issuing the Precharge of Burst Stop Command
CASE I ) Issued read Interrupt command during burst read operation period.
CLK CMD Data(CL2) Data(CL3) Data(CL4) RD PRE
(1)
CLK CMD DQ1 DQ0 DQ1 DQ0 DQ1 Data(CL2) Data(CL3) Data(CL4) RD
STOP
(1)
DQ0
DQ0
DQ1 DQ0 DQ1 DQ0 DQ1
CASE II ) Issued read Interrupt command between read command and data out.
CLK CMD Data(CL2) Data(CL3) Data(CL4) RD PRE
(2)
CLK CMD DQ0 DQ0 DQ0 Data(CL2) Data(CL3) Data(CL4) RD
STOP
(2)
DQ0 DQ0 DQ0
Notes:
1. The data bus goes to high-Z after CAS latency from the Burst Stop (or precharge) command. 2. Valid output data will last up to CL-1 clock cycle from PRE command.
28
AT49LD3200(B)
1940B-FLASH-11/01
AT49LD3200(B)
Read Cycle Depending on tRC
@RL = 2, CL = 6, BL = 4; 100 MHz
CLK
tRC(min)=7 tCC=10ns
CMD
ACT
RDa
ACT ACT
RDb
CASE I ) CASE II ) CASE III )
RDb ACT
RDb
CASE I ) CASE II ) CASE III )
High-Z DQa0 DQa1 DQa2 DQa3 DQa0 DQa1 DQa2 DQa3
DQb0 DQb1 DQb2 DQb3 DQb0 DQb1 DQb2 DQb3 DQb0 DQb1 DQb2 DQb3
@RL = 2, CL = 5, BL = 4; 75 MHz
CLK
tRC(min)=6 tCC=15ns
CMD
ACT
RDa
ACT ACT
RDb
CASE I ) CASE II ) CASE III )
RDb ACT
RDb
CASE I ) CASE II ) CASE III )
High-Z DQa0 DQa1 DQa2 DQa3 DQa0 DQa1 DQa2 DQa3
DQb0 DQb1 DQb2 DQb3 DQb0 DQb1 DQb2 DQb3 DQb0 DQb1 DQb2 DQb3
@RL = 1, CL = 4, BL = 4; 50 MHz
CLK
tRC(min)=4 tCC=20ns
CMD
ACT
RDa
ACT RDb
CASE I ) CASE II) CASE III)
ACT RDb
ACT RDb CASE I ) CASE II ) CASE III )
DQb0 DQb1 DQb2 DQb3 DQa0 DQa1 DQa2 DQa3 DQb0 DQb1 DQb2 DQb3 DQa0 DQa1 DQa2 DQa3
(Gapless Operation)
DQb0 DQb1 DQb2 DQb3
29
1940B-FLASH-11/01
Read Cycle Depending on tVCVC
@RL = 2, CL = 6, BL = 4; 100 MHz
CLK
tVCVC=5 tCC=10ns
CMD
ACT
RDa
RDb
CASE I) CASE II) CASE III)
RDb
RDb CASE I ) CASE II ) CASE III )
DQb0 DQb1 DQb2 DQb3
(Gapless Operation)
DQa0 DQa1 DQa2 DQa3 DQb0 DQb1 DQb2 DQb3 DQa0 DQa1 DQa2 DQa3 DQb0 DQb1 DQb2 DQb3
@RL = 2, CL = 5, BL = 4; 75 MHz
CLK
tVCVC=4 tCC=15ns
CMD
ACT
RDa
RDb
CASE I) CASE II) CASE III)
RDb
RDb CASE I ) CASE II ) CASE III )
DQb0 DQb1 DQb2 DQb3
(Gapless Operation)
DQa0 DQa1 DQa2 DQa3 DQb0 DQb1 DQb2 DQb3 DQa0 DQa1 DQa2 DQa3 DQb0 DQb1 DQb2 DQb3
@RL = 1, CL = 4, BL = 4; 50 MHz
CLK
tVCVC=3 tCC=20ns
CMD
ACT
RDa
RDb
CASE I) CASE II) CASE III)
RDb
RDb CASE I ) CASE II ) CASE III )
DQb0 DQb1 DQb2 DQb3 DQa0 DQa1 DQa2 DQb1 DQb2 DQb3
(Gapless Operation)
DQa0 DQa1 DQa2 DQa3 DQb0 DQb1 DQb2 DQb3 : Invalid Data
30
AT49LD3200(B)
1940B-FLASH-11/01
AT49LD3200(B)
AC Characteristics for Boot Block Read Operation
Symbol tACC tOE tDF tOH Parameter Address to Output Delay DQM to Output Delay DQM High to Output Float Output Hold from Address 0 Condition CS = DQM = VIL CS = VIL Min Max 170 60 40 Units ns ns ns ns
AC Waveforms for Boot Block Read Operation
ADDRESS ADDRESS VALID
CS
tOE DQM tACC OUTPUT HIGH-Z tOH OUTPUT VALID tDF
31
1940B-FLASH-11/01
l
3-volt Program and Erase Cycle Characteristics
Symbol tPGM tEC tBBL ICC2 Parameter Word/Double Word Programming Time Sector/Boot Block Erase Cycle Time Boot Block Lockout Enable Time VCC Current during Program and Erase Cycle Typ 50 Max 600 2.0/300 10 150 Units s seconds/ms ms mA
High-speed 12-volt Program and Erase Cycle Characteristics
Symbol tPGM tEC ICC3 IPP3 Parameter Word/Double Word Programming Time Sector/Boot Block Erase Cycle Time VCC Current During Program and Erase Cycle VPP Current During Program and Erase Cycle Typ 15 Max 200 1.2/200 75 75 Units s seconds/ms mA mA
Program Cycle Waveforms
PROGRAM CYCLE CLK
CS tPGM WE
RAS CAS
ADDR
AA
55
55
2A
AA
55
RA
CA
DATA
AA
PRECHARGE COMMAND
55
PRECHARGE COMMAND
A0
PRECHARGE COMMAND
DIN
PRECHARGE COMMAND
Sector Erase Cycle Waveforms
SECTOR ERASE CYCLE CLK
CS tEC WE
RAS CAS
ADDR
AA
55
55
2A
AA
55
AA
55
55
2A
SA
X
DATA
AA
PRECHARGE COMMAND
55
PRECHARGE COMMAND
80
PRECHARGE COMMAND
AA
PRECHARGE COMMAND
55
PRECHARGE COMMAND
30
PRECHARGE COMMAND
Notes:
1. The Precharge command is optional. A Precharge command (CS, RAS, MR = L) during Program and Sector Erase cycles (WE = L) will be treated as NOP, and the number of clock cycles between the bus cycle and the Precharge command or vice versa should be "Don't Care". 2. For boot block programming, RA = CA = A0 ~ A12 and be held valid throughout program cycle; DQM should be held "H" during the four-bus cycle command operation. 3. For boot block erasing, SA = X; DQM should be held "H" during the six-bus cycle command operation.
32
AT49LD3200(B)
1940B-FLASH-11/01
AT49LD3200(B)
Data Polling Waveforms
tPGM/tEC CLK
DQM
CS
WE
RAS
CAS RA CA RA CA
ADDR
DQ7 (RL2, CL5, BL4)
READ (DATA POLLING)
DATA
READ
DATA
Note:
During Program cycle, DATA = complement of loaded DQ7. After Program cycle, DATA = same state as loaded DQ7. During Sector Erase cycle, DATA = "0"; after Sector Erase cycle, DATA = "1".
Data Polling Waveforms for Boot Block
tPGM/tEC CLK
DQM
CS
WE
RAS
CAS VALID ADDRESS READ (DATA POLLING)
ADDR
DQ7 (RL2, CL5, BL4)
DATA
READ
DATA
Note:
During Program cycle, DATA = complement of loaded DQ7. After Program cycle, DATA = same state as loaded DQ7. During Sector Erase cycle, DATA = "0"; after Sector Erase cycle, DATA = "1".
33
1940B-FLASH-11/01
Product ID Cycle Waveforms
PRODUCT ID CYCLE CLK DQM CS WE RAS CAS
ADDR DATA (CL5, BL4, X16) DATA (CL5, BL4, X32) MR
A7 MC DC C
MRS
READ
Note:
For x16 Mode, Manufacturer Code, MC = 001F(HEX), Device Code, DC = 32C2 (HEX). For x32 Mode, Code, C = 32C2001F (HEX).
Continuity Test Mode Entry Waveforms
CLK
DQM
CS
WE
RAS
CAS
ADDR
AA
55
55
2A
AA
55
AA
55
AA
55
DATA
AA
PRECHARGE COMMAND
55
PRECHARGE COMMAND
80
PRECHARGE COMMAND
AA
PRECHARGE COMMAND
70
34
AT49LD3200(B)
1940B-FLASH-11/01
AT49LD3200(B)
Boot Block Lockout Cycle Waveforms
BOOT BLOCK LOCKOUT CYCLE CLK
CS tBBL WE
RAS CAS
ADDR
AA
55
55
2A
AA
55
AA
55
AA
55
DATA
AA
PRECHARGE COMMAND
55
PRECHARGE COMMAND
80
PRECHARGE COMMAND
AA
PRECHARGE COMMAND
40
PRECHARGE COMMAND
Boot Block Lockout Verify Cycle Waveforms
BOOT BLOCK LOCKOUT VERIFY CYCLE CLK 200 ns CS
WE
RAS
CAS
ADDR
AA
55
55
2A
AA
55
AA
55
AA
55
DATA (CL5, BL4)
AA
PRECHARGE COMMAND
55
PRECHARGE COMMAND
80
PRECHARGE COMMAND
AA
PRECHARGE COMMAND
90
PRECHARGE COMMAND
READ
DQ
Note:
DQ = XX00 (Hex) implies Boot Block not activated and Lockout not enabled. DQ = XX01 (Hex) implies Boot Block not activated and Lockout enabled. DQ = XX02 (Hex) implies Boot Block activated and Lockout not enabled. DQ = XX03 (Hex) implies Boot Block activated and Lockout enabled.
35
1940B-FLASH-11/01
Boot Block Lockout Verify Exit Cycle Waveforms
BOOT BLOCK LOCKOUT VERIFY EXIT CYCLE CLK
CS 10 s WE
RAS CAS
ADDR
AA
55
55
2A
AA
55
AA
55
AA
55
DATA
AA
PRECHARGE COMMAND
55
PRECHARGE COMMAND
80
PRECHARGE COMMAND
AA
PRECHARGE COMMAND
F0
PRECHARGE COMMAND
36
AT49LD3200(B)
1940B-FLASH-11/01
AT49LD3200(B)
Ordering Information
Max Freq (MHz) 100 ICC (mA) Active 150 150 75 150 150 50 150 150 Standby 0.05 0.05 0.05 0.05 0.05 0.05 Ordering Code AT49LD3200-10TC AT49LD3200-10TI AT49LD3200-13TC AT49LD3200-13TI AT49LD3200-20TC AT49LD3200-20TI Package 86T 86T 86T 86T 86T 86T Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C)
Package Type 86T 86-lead, Thin Small Outline Package (TSOP Type II)
37
1940B-FLASH-11/01
Packaging Information
86T - TSOP Type II
0 ~ 8 c
E1 PIN 1 Identifier
E L L1
PIN 1
b SEATING PLANE D A GAGE PLANE
e
A1
A2
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 MIN - 0.05 0.95 22.12 11.56 10.06 0.40 NOM - - 1.00 22.22 11.76 10.16 0.50 0.25 BASIC 0.17 0.12 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 22.32 11.96 10.26 0.60 Note 2 Note 2 NOTE
Notes:
1. This package conforms to JEDEC reference MO-142, Variation EC. 2. Dimensions D and E1 do not include mold protrusion. Allowable protrusion on E1 is 0.25 mm per side and on D is 0.15 mm per side. 3. Lead coplanarity is 0.10 mm maximum.
D E E1 L L1 b c e
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 86T, 86-lead (10.16 mm Body Width) Thin Small Outline Package (TSOP Type ll) DRAWING NO. 86T REV. B
R
38
AT49LD3200(B)
1940B-FLASH-11/01
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. SFlash TM is a trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
1940B-FLASH-11/01 /xM

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